Static electricity poses a severe threat to the delicate components within an integrated circuit (IC) package. On a dry day, 30,000 volts can jump a centimeter from a human body to an IC package being handled, thereby destroying the chip. As IC technology improves, more devices are installed on each chip. This means that a proportionately smaller voltage can damage the chip.
Integrated circuits used today must meet both commercial and military standards which specify a human body model electrostatic discharge (ESD) test. The model determines the amount of electrostatic discharge that an integrated circuit can absorb without damage. Since electrostatic discharge is imparted to the integrated circuit during normal handling of a chip, and to the boards containing the integrated circuit chips, it is desirable that the integrated circuits are able to absorb as much electrostatic discharge as possible without causing damage thereto.
A previously developed technique used to protect a circuit gate from ESD stress is to use a fast switching initial protection device near the circuit gate to clamp any ESD voltage. Typically, the initial protection device triggers quickly and begins to dissipate the ESD pulse. However, the pulse is often too large in amplitude for the initial protection device to fully dissipate. Therefore, a "primary" switching device is often provided to share the surge placed across the initial protection device. Indeed, the primary switching device is typically selected so that it will bear most of the burden in dissipating the ESD pulse. However, this primary switching device will take longer to fire (i.e. to enable) than the initial protection device. Therefore, a resistance is built between the two devices in order to maintain a voltage such that the primary switching device has time to trigger after a predetermined voltage is present across the resistor.
The resistance between the initial protection device and the primary switching device is typically constructed by standard semiconductor fabrication processes. As a result, one or more PN junctions are formed as a part of the resistor. The existence of these junctions gives rise to areas of potential voltage breakdown. If a PN junction of the resistor breaks down during an ESD operation, the resistor will leak current through the breakdown region. Since less current will flow through the resistor, the voltage across the resistor will correspondingly decrease. If the voltage loss is severe, then the resistor may not maintain a large enough voltage to enable the primary switching device. This can force the initial protection device to absorb excessive energy and hence destroy it. Also, the voltage may cause breakdown of the circuit being protected. Thus, the breakdown of the resistor can cause the protection circuit to fail to properly operate. This may cause damage to the initial protection device, and to the chip which was otherwise intended to be protected from an ESD pulse.
Therefore, a need has arisen for a protection circuit which will better insure dissipation of an ESD pulse. More particularly, there is a need for a protection scheme which will insure that the primary switching device is enabled to thereby fully dissipate an ESD pulse.